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The Model 2004 charge sensitive FET input preamplifier was designed for use with both low and high capacitance semiconductor detectors. The preamp converts the charge carriers developed in the detector during each absorbed nuclear event to a step function voltage pulse, the amplitude of which is proportional to the total charge accumulated in that event. The output provides a positive polarity signal when used with detectors requiring positive bias and decays with a nominal time constant of 50 ms.
The high charge rate capability of the design is evidenced by a charge rate capacity of better than 2 x 10-7 coulombs per second, or 4.5 x 106 MeV per second for silicon detectors. In order to take full advantage of such a high count rate capability, a main amplifier with a correspondingly high count rate ability, such as the Mirion Model 2020 amplifier, should be employed.
As shown in the functional schematic, the first stage acts as an operational integrator which produces an output potential proportional to the accumulated charge. This integrator is coupled to an output buffer stage through a pole/zero trim network. A feature of particular importance to certain users is a removable socketed resistor on the printed circuit board for disabling the pole/zero circuit. For low count rate applications using high leakage detectors, the resulting low frequency noise bandwidth may improve resolution.
The preamplifier offers a noise contribution of only 2.8 keV, FWHM, Si, with a rate of noise increase with increasing input capacitance of only 10 eV per picofarad, FWHM, Si. Conversion gains of nominally 9 mV per MeV or 45 mV per MeV (Si) may be selected by a jumper plug on the printed circuit board inside the unit.
In addition, the input circuit includes a protection network to prevent damage to the input FET from transient high voltage waveforms caused by sudden application or removal of detector bias, or a detector fault. All necessary power is provided by a Mirion main amplifier through the 300 cm (ten ft.) compatible cable.